1) Field of the Invention
The present invention relates to a memory control device, a move-in buffer control method, and a program. More particularly, the present invention relates to a memory control device and a move-in buffer control method that can efficiently control a reference to data stored in a main storage.
2) Description of the Related Art
Conventionally, the operation speed of a central processor is much faster than the operation speed of a main storage, which raises a problem that when the main storage is referred to, the operation of the central processor must wait for a long time.
In order to solve this problem, there is disclosed a conventional technique of avoiding a stalled execution of a central processor due to reference to data stored in a main storage, using a prefetch command to fetch data to be used later to a cache in advance. In other words, when a demand request, which is a processing of the central processor to wait for a completion of reference to data stored in a cache or the main storage, is executed, such as a load command to store data fetched from the cache or the main storage into an operation device, and a store command to write an operation result into the cache or the main storage, a cache line that is necessary for the demand request is prepared on the cache in advance based on the prefetch command. With this arrangement, the stalled execution of the central processor due to the reference to data stored in the main storage can be avoided.
There is also disclosed a conventional technique of shortening the time of waiting for fetching data from the main storage, that is, memory latency, by executing a request for reference to data stored in the cache or the main storage by an out-of-order processing. In other words, in the out-of-order processing, executable commands are executed first instead of executing the commands in the sequence of a program. For example, while fetching of data from the main storage is awaited due to a cache miss caused by a precedent command, a succeeding command is executed. When the succeeding command causes a cache hit, the data fetched from the cache is stored into a register of the operation device. An operation is carried out using the stored data, and the execution of the program is progressed within a possible range. When the succeeding command causes a cache miss, a necessary cache line is fetched from the main storage. When a plurality of cache misses are processed simultaneously, the memory latency can be shortened, as compared with the case of sequentially processing cache misses.
A cache MIB (“move-in buffer” is hereinafter referred to as an MIB (Move In Buffer)) is provided for each cache. In fetching a cache line from the main storage due to the occurrence of a cache miss, by storing a physical address of the cache line in the reference request, the time from the assigning of the cache MIBs till the completion of the transfer to the cache can be shortened. Requesting for a plurality of references to the same address is avoided. Unnecessary assigning of the cache MIBs is avoided, and unnecessary use of data transfer buses due to data transfer is avoided.
On the other hand, when referring to much data according to a program of carrying out operation by referring to a multidimensional array, many cache lines must be fetched to the primary cache based on a prefetch command. Therefore, depletion of the primary cache MIBs of the primary cache occurs frequently. In this case, even if a demand request tries to assign the primary cache MIBs, the primary cache MIBs cannot be assigned. Therefore, the execution of the demand request must wait until some primary cache MIBs become available. In other words, based on the prefetch request for preparing data that is considered to become necessary later, a demand request that requires an immediate completion of the execution is interrupted. As a result, reference to data stored in the main storage cannot be controlled efficiently.
When the succeeding load requests or store requests assign the entire primary cache MIBs based on the out-of-order processing, a load request or a store request that must be executed first in executing the command cannot assign the primary cache MIBs, and the execution of the command is interrupted. As a result, reference to data stored in the main storage cannot be controlled efficiently.
When the succeeding load requests or store requests assign the primary cache MIBs first based on the out-of-order processing, and when a slashing of the cache line occurs, execution of a load request or a store request that must be executed first in executing the command must wait for a long time. As a result, reference to data stored in the main storage cannot be controlled efficiently.
Japanese Patent Application Laid-Open No. H4-21044 discloses a conventional technique of improving system performance by increasing the number of times of prefetching commands to be loaded on the cache more than the number of times of prefetching operands. Japanese Patent Application Laid-Open No. H6-90681 discloses a conventional technique of executing prefetch by an optional number of times requested within a maximum permissible number of times of block fetch. Japanese Patent Application Laid-Open No. H8-16468 discloses a conventional technique of preventing depletion of the primary cache MIBs by deleting unnecessary prefetch.
According to the conventional technique disclosed in Japanese Patent Application Laid-Open No. H4-21044, system performance can be improved by increasing the number of prefetching commands to be loaded on the cache to more than the number of prefetching operands. According to the conventional technique disclosed in Japanese Patent Application Laid-Open No. 64-46145, prefetch can be executed by an optional number of times requested within a maximum permissible number of times of block fetch. According to the conventional technique disclosed in Japanese Patent Application Laid-Open No. H8-16468, depletion of the primary cache MIBs can be prevented by deleting unnecessary prefetch.
However, according the conventional techniques disclosed in the above-mentioned patent application, exclusive use of the primary cache MIBs by the prefetch command cannot be avoided. Therefore, demand request that requires an immediate completion of the execution is interrupted by the prefetch request for preparing data that is considered to become necessary later. As a result, the problem that reference to data stored in the main storage cannot be controlled efficiently remains unsolved.
When the succeeding load requests or store requests assign the entire primary cache MIBs based on the out-of-order processing, a load request or a store request that must be executed first in executing the command cannot assign the primary cache MIBs, and the execution of the command is interrupted. As a result, the problem that reference to data stored in the main storage cannot be controlled efficiently remains unsolved.
When the succeeding load requests or store requests-assign the primary-cache MIBs first based on the out-of-order processing, and when a slashing of the cache line occurs, execution of a load request or a store request that must be executed first in executing the command must wait for a long time. As a result, the problem that reference to data stored in the main storage cannot be controlled efficiently remains unsolved.